A power loss due to the edge-alignment phase shift and a power loss due to the overlap phase shift can be estimated by simulation, or the like. FIG. 12 and FIG. 13 illustrate time charts for estimating power losses at the time when the respective phase shifts shown in FIG. 11 are executed. For the sake of convenience of the drawing, the time charts from PWM2₀ to PWM2₁ are excerpted and shown.

From the top of the time chart of FIG. 12, /PWM1, /PWM2 respectively denote the inversion signals of PWM1, PWM2. The fluctuations in these signals are predicted by obtaining the above-described rates. S1 PWM to S4 PWM respectively denote the PWM signals that are transmitted to the switching elements S1 to S4. In addition to the on/off states of the switching elements S1 to S4, current components in the on state are shown to the right of S1 PWM to S4 PWM.

Inscriptions, such as (/1+2), denote superimposed signals of the PWM signals PWM1, PWM2, which are transmitted to the corresponding switching elements. For example, in the case of (/1+2), the PWM signals of /PWM1 and PWM2 are superimposed. In addition, an operation mode at the bottom indicates the charge/discharge mode of each of the first, step-up/step-down circuit CNV1 and the second step-up/step-down circuit CNV2 at each time. C1, C2 respectively denote the first and second step-up/step-down circuits CNV1, CNV2, the suffix _C denotes the charge mode, and the suffix _D denotes the discharge mode.