High speed DFEs with direct feedback
地域：
NY
NY Armonk
摘要
A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.
說明書
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This invention was made with Government support under Contract No. H98230-12-C-0325 with Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention.
The present disclosure generally relates to equalization techniques for high-speed data communications, and more particularly, to implementations of decision feedback equalizer (DFE) circuits with improved performance.
Over the years, demand for high-bandwidth transmission of data has continuously increased. However, the limited bandwidth of electrical communication channels makes it difficult to increase data rates without approaching reliability roadblocks. Channel bandwidth degradation may result due to various physical effects, including skin effect, dielectric loss, and reflections due to impedance discontinuities. As real world communication channels are stressed with higher data rates, intersymbol interference (ISI) becomes a limiting factor. High data rate pulses transmitted through these channels broaden to greater than a unit interval (UI), thereby creating ISI with preceding bits (precursors) and succeeding bits (postcursors).
權利要求
What is claimed is:1. A decision feedback equalizer (DFE), comprising:a plurality of paths, each path having at least one adding slicer comprising:a decision-making slicer circuit comprising a first input, a second input coupled to a first clock signal that initiates a decision-making phase of the decision-making slicer circuit at a first edge of the first clock signal, an output, and a current injection input; and a plurality of adder circuits, each having an input operative to receive a respective bit of a digital code representing a previously decided symbol, fed back from an output of a prior path of the plurality of paths, and an input coupled to a second clock signal, wherein:the plurality of adder circuits are collectively configured to inject an offset current proportional to the digital code representing the previously decided symbol into the current injection input at a first edge of the second clock signal, and there is a predetermined skew between the first clock signal and the second clock signal to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of the decision-making phase of the decision-making slicer circuit. 2. The DFE of claim 1 , wherein the DFE is configured to receive PAM4 input signals. 3. The DFE of claim 1 , wherein the predetermined skew between the first clock signal and the second clock signal adjusts the timing of the injection of the offset current into the current injection input such that the injection is before the initiation of the decision-making phase. 4. The DFE of claim 1 , wherein the decision-making slicer circuit further comprises a reference input. 5. The DFE of claim 4 , wherein:the first input of the decision-making slicer is differential; the reference input is differential; the output of the decision-making slicer is differential; the current injection input is a differential input having a first node and a second node; and the digital code received by the plurality of adder circuits is a differential thermometer code. 6. The DFE of claim 5 , wherein the plurality of paths comprises:a first path having three parallel adding slicers, each adding slicer having three adder circuits configured to receive the differential thermometer code from an output of a fourth path; a second path having three parallel adding slicers, each adding slicer having three adder circuits configured to receive the differential thermometer code from an output of the first path; a third path having three parallel adding slicers, each adding slicer having three adder circuits configured to receive the differential thermometer code from an output of the second path; and the fourth path having three parallel adding slicers, each adding slicer having three adder circuits configured to receive the differential thermometer code from an output of the third path. 7. The DFE of claim 5 :wherein each decision-making slicer circuit comprises:an input stage comprising two differential pairs configured to receive a differential input voltage at the first differential input and a differential reference voltage at the reference differential input; and a set of cross-coupled inverters forming a latching circuit and configured to provide a rail to rail differential signal at the differential output, wherein each decision-making slicer is configured to determine whether to provide a differential 1 or 0 at the differential output upon comparing the differential input voltage to the differential reference voltage after receiving the injected offset current at the differential current injection input, and wherein receipt of the injected offset current shifts a threshold of the decision-making slicer circuit up or down depending on a polarity of the injected offset current. 8. The DFE of claim 7 , wherein a size of the shift of the threshold of the decision-making slicer circuit is based on a magnitude of the injected offset current. 9. The DFE of claim 7 , wherein the input stage comprises:a first transistor having a source coupled to a first supply and a gate coupled to the first clock signal, a second transistor having a source coupled to a drain of the first transistor, a gate coupled to a positive side of the differential reference input, and a drain coupled to the second current injection node; a third transistor having a source coupled to the drain of the first transistor, a gate coupled to a positive side of the differential input, and a drain coupled to the first current injection node; a fourth transistor having a source coupled to the first supply and a gate coupled to the first clock signal; a fifth transistor having a source coupled to a drain of the fourth transistor, a gate coupled to a negative side of the differential reference input, and a drain coupled to the first current injection node; and a sixth transistor having a source coupled to the drain of the fourth transistor, a gate coupled to the negative side of the differential input, and a drain coupled to the second current injection node. 10. The DFE of claim 7 , wherein the set of cross-coupled inverters comprises:a first transistor having a source coupled to the first current injection node, a drain coupled to a negative side of a differential output, and a gate coupled to a positive side of the differential output; a second transistor having a drain coupled to the negative side of the differential output, a gate coupled to the positive side of the differential output, and a source coupled to a second supply; and a third transistor having a drain coupled to the negative side of the differential output, a gate coupled to the first clock signal, and a source coupled to the second supply; a fourth transistor having a source coupled to the second current injection node, a drain coupled to the positive side of a differential output, and a gate coupled to the negative side of the differential output; a fifth transistor having a drain coupled to the positive side of the differential output, a gate coupled to the negative side of the differential output, and a source coupled to the second supply; and a sixth transistor having a drain coupled to the positive side of the differential output, a gate coupled to the first clock signal, and a source coupled to the second supply. 11. The DFE of claim 5 , wherein each adder circuit comprises:a first current source having a first node coupled to a first supply; a first transistor having a source coupled to a second node of the first current source, and a gate coupled to the second clock; a second transistor having a source coupled to a drain of the first transistor, a gate configured to turn ON or OFF the second transistor, and a drain coupled to the second current injection node; and a third transistor having a source coupled to the drain of the first transistor, a gate configured to turn ON or OFF the third transistor, and a drain coupled to the first current injection node, wherein the gates of the second and third transistors are configured to receive a respective differential bit of the differential thermometer code. 12. The DFE of claim 11 , wherein each adder circuit further comprises a fourth transistor having a source coupled to the second node of the first current source, a drain coupled to the second supply, and a gate coupled to an inverse of the second clock. 13. The DFE of claim 11 , wherein each adder circuit further comprises:a second current source having a first node coupled to the first supply; a fourth transistor having a source coupled to a second node of the second current source, and a gate coupled to the second clock; a fifth transistor having a source coupled to a drain of the fourth transistor, a gate configured to turn ON or OFF the fifth transistor, and a drain coupled to the first current injection node; and a sixth transistor having a source coupled to the drain of the fourth transistor, a gate configured to turn ON or OFF the sixth transistor, and a drain coupled to the second current injection node, wherein the gates of the fifth and sixth transistors are configured to receive a respective differential bit of the differential thermometer code. 14. The DFE of claim 13 , wherein each adder circuit further comprises:a seventh transistor having a source coupled to the second node of the first current source, a drain coupled to the second supply, and a gate coupled to an inverse of the second clock; and an eighth transistor having a source coupled to the second node of the second current source, a drain coupled to the second supply, and a gate coupled to the inverse of the second clock. 15. The DFE of claim 5 , further comprising a thermometer to binary converter coupled to the differential output of each path, respectively. 16. The DFE of claim 5 , wherein a level of the differential reference input is programmable. 17. A method of equalizing in a decision feedback equalizer having a plurality of paths, the method comprising:receiving, by a plurality of adder circuits, a digital code representing a previously decided symbol from an output of a prior path of the plurality of paths, wherein each adder circuit receives a respective bit of the digital code; receiving, by a decision-making slicer circuit, an input voltage; receiving, by the decision-making slicer circuit, a first clock signal operative to initiate a decision-making phase of the decision-making slicer circuit; receiving, by the plurality of adder circuits, a second clock signal operative to initiate an injection of an offset current into a current injection input of the decision-making slicer circuit; injecting, by the plurality of adder circuits, the offset current proportional to the digital code representing the previously decided symbol into the current injection input, at a first edge of the second clock signal; and introducing a predetermined skew between the first clock signal and the second clock signal. 18. The method of claim 17 , wherein:the digital code representing the previously decided symbol received by the plurality of adder circuits is a differential thermometer code; the input voltage received by the decision-making slicer circuit is differential; and the injected offset current proportional to the digital code is differential. 19. The method of claim 18 , further comprising:receiving, by the decision-making slicer circuit, a differential reference voltage; and comparing, by the decision-making slicer circuit, the differential input voltage to the differential reference voltage, after receiving the offset current proportional to the digital code representing the previously decided symbol, wherein receipt of the injected offset current shifts a threshold of the decision-making slicer circuit, up or down, depending on a polarity of the injected offset current. 20. The method of claim 19 , wherein a size of the shift of the threshold of the decision-making slicer circuit is based on a magnitude of the injected offset current. 21. The method of claim 18 , wherein the received differential input signal is a PAM4 signal. 22. The method of claim 17 , wherein the predetermined skew between the first clock signal and the second clock signal is such that the injection of the offset current is before the initiation of the decision-making phase. 23. A decision feedback equalizer (DFE), comprising:a plurality of paths, each path having at least one adding slicer comprising:a decision-making slicer circuit comprising a first input, a second input coupled to a first clock signal that initiates a decision-making phase of the decision-making slicer circuit at a first edge of the first clock signal, an output, and a current injection input; and an adder circuit having an input operative to receive a respective bit of a digital code representing a previously decided symbol, fed back from an output of a prior path of the plurality of paths, and an input coupled to a second clock signal, wherein: the adder circuit is configured to inject an offset current proportional to the digital code representing the previously decided symbol into the current injection input at a first edge of the second clock signal, and there is a predetermined skew between the first clock signal and the second clock signal to control a timing between the injection of the offset current of the adder circuit and the initiation of the decision-making phase of the decision-making slicer circuit. 24. The DFE of claim 23 , wherein the DFE is configured to receive non-return-to-zero (NRZ) signals at its first input.
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