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High speed DFEs with direct feedback

專利號
US10097383B1
公開日期
2018-10-09
申請人
International Business Machines Corporation（US NY Armonk）
發(fā)明人
John Bulzacchelli; Timothy Dickson; Mounir Meghelli; Jonathan Proesel; Guanghua Shu
IPC分類
H04L25/03
技術(shù)領(lǐng)域
slicer,dfe,decision,clk90,adder,pam4,tap,current,clock,h1p
地域： NY NY Armonk

摘要

A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

說明書

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

權(quán)利要求

1
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