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High speed DFEs with direct feedback

專(zhuān)利號(hào)
US10097383B1
公開(kāi)日期
2018-10-09
申請(qǐng)人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
John Bulzacchelli; Timothy Dickson; Mounir Meghelli; Jonathan Proesel; Guanghua Shu
IPC分類(lèi)
H04L25/03
技術(shù)領(lǐng)域
slicer,dfe,decision,clk90,adder,pam4,tap,current,clock,h1p
地域: NY NY Armonk

摘要

A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

說(shuō)明書(shū)

In one aspect, the decision-making slicer circuit 450 is essentially a highly sensitive latch. The decision-making slicer 450 includes a clocked differential input comparator stage 401, referred to herein as an input stage, comprising transistors 406A-408A and 406B-408B. It produces a differential output at the output nodes QN90 and QP90, depending on whether the differential input voltage VIP?VIN is above or below the differential reference voltage VREFP?VREFN. In some embodiments, the voltage levels of VREFP and VREFN are programmable, thereby allowing to set different thresholds. For a PAM4 system, there would be 3 of such adding slicers 400 to discern the four different voltage levels.

Accordingly, the input stage of the decision-making slicer circuit 450 uses a couple of differential pairs in the input stage having two differential pairs 401 (rather than a single differential pair) connected as a differential comparator structure, so that the input-referred threshold of the latch can be adjusted by setting reference voltages VREFP and VREFN. In particular, the latch makes a binary “one” decision when the differential input voltage (VIP?VIN) exceeds VREFP?VREFN and makes a binary “zero” decision when the differential input voltage (VIP?VIN) is below VREFP?VREFN. This binary decision appears at the regenerative output nodes (QP90 and QN90) a short time after the latch is activated (by switching CLK90 low). Here the differential comparator structure of the input stage 401 is used to set the threshold to a value between two of the levels of the received PAM4 signal.

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