The input stage 401 is configured to receive a differential input voltage V_IP/V_IN, a differential reference voltage V_REFP/V_REFN, and a first clock signal CLK₉₀. When transistors 402A/B are ON (i.e., CLK90 is low), the differential input voltage V_IP V_IN is compared to the differential reference voltage V_REFP?V_REFN to determine whether the differential signal at the differential input nodes is above (or below) the latch threshold and a binary “one” (or “zero”) decision should be made. The first side (e.g., left) of the input stage 401 comprises a first transistor 402A having a source coupled to a first supply (e.g., V_DD) and a gate coupled to first clock signal (CLK₉₀). The second transistor 406A has a source coupled to the drain of the first transistor 402A, a gate coupled to a positive side of the differential reference voltage V_REFP, and a drain coupled to the second current injection node 420B (H1P₉₀). The third transistor 408A has a source coupled to the drain of the first transistor 402A, a gate coupled to a positive side of the differential input voltage V_IP, and a drain coupled to the first current injection node 420A (H1N₉₀). In one embodiment, there is a current source 404A. The second differential pair of the input stage 401 has substantially similar components.