High speed DFEs with direct feedback
摘要
說明書
However, for an intermediate PAM4 signal level (which is not max or min), an intermediate level of compensation is achieved because two of the adders route the H1P/3 current in one direction, while the remaining adder routes the H1P/3 current in the other direction. Thus, the compensation is proportional to the symbol that is being compensated.
Accordingly, each output of an adder circuit 430(0) to 430(2), is injected directly into the current injection nodes 420A and 420B of its corresponding decision-making slicer circuit 450. Significantly, a summing amplifier to sum the currents of the prior quadrant (i.e., provided via the adder circuits 430(0) to 430(2)), need not be used, thereby simplifying the architecture and improving the performance (i.e., speed) of a DFE. Thus, by virtue of injecting the DFE current, provided by the adder circuits 430(0) to 430(2) directly into the current injection nodes of the decision-making slicer, latency is reduced, and the DFE can be operated with high accuracy at enhanced operating speeds.
