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High speed DFEs with direct feedback

專利號
US10097383B1
公開日期
2018-10-09
申請人
International Business Machines Corporation(US NY Armonk)
發(fā)明人
John Bulzacchelli; Timothy Dickson; Mounir Meghelli; Jonathan Proesel; Guanghua Shu
IPC分類
H04L25/03
技術(shù)領(lǐng)域
slicer,dfe,decision,clk90,adder,pam4,tap,current,clock,h1p
地域: NY NY Armonk

摘要

A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

說明書

While FIGS. 4 and 5A illustrate differential architectures by way of example, single ended implementations are within the scope and spirit of the present disclosure. In one embodiment, a reference voltage signal is not provided. For example, a decision-making slicer circuit for an NRZ system may operate without such differential reference voltage signal. To that end, FIG. 5B illustrates an adding slicer 500B without a reference input, consistent with an illustrative embodiment. By way of comparative example, adding slicer 500B does not include components 502B, 504B, 506B, and 508B. Further, it only includes a single adder circuit 530(0). Instead of relying on the differential reference voltage input VREFp/VREFN, the adding slicer 500B simply evaluates the VIP?VIN differential signal via the input stage 501.

Clock Skew Between the Clocks of the Slicer and the 1 Tap DFE Feedback Circuit

權(quán)利要求

1
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