Accordingly, in general, a larger T_skew yields a larger tap weight. However, a larger value of T_skew also entails a feedback loop delay penalty. Referring back to FIG. 6, the delay between the falling edge of CLK₀ and the data output Q₀[2:0] (referred to herein as the T_clk-to-Q delay 604) becoming valid equals the clock-to-Q delay of the decision-making slicer circuit 550. In a quarter-rate system, the quarter-rate clocks CLK₀, CLK₉₀, CLK₁₈₀, and CLK₂₇₀ are shifted by one unit interval (UI) with respect to each other, so the time between the falling edge of CLK₀ and the falling edge of CLK₉₀ equals 1UI. For the RZ tap to operate with the intended benefits, the Q₀[2:0] data should arrive at the tap circuits before CLK_IH1 (in this case, CLK_{IH1_90}) is switched low. If the setup time T_setup 606 is defined as the time between the arrival of the valid Q₀[2:0] data and the falling edge of CLK_{IH1_90}, it follows that:
T_setup=1UI?T_clk-to-Q?T_skew??(Eq. 1)

Note that both the clock-to-Q delay of the decision-making slicer circuit 550 and T_skew subtract from the available setup time for the DFE feedback tap circuit. Since T_setup is positive (or nearly positive) for proper operation of the RZ tap circuit, there is an upper limit on the choice of T_skew, which can be chosen as a compromise between tap weight strength and feedback timing margins, as discussed in the context of FIG. 7.