FIG. 8 is an example floorplan of a quarter-rate architecture PAM4 DFE, consistent with an illustrative embodiment.

FIG. 9 illustrates an example graph of a DFE tap weight versus a differential tap weight current.

In the following detailed description, numerous specific details are set forth by way of examples to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, to avoid unnecessarily obscuring aspects of the present teachings.

The present disclosure relates to systems, circuits, and methods of implementing a decision feedback equalizer with a low bit error rate (BER). In a DFE, previous data decisions, sometimes referred to herein as symbols, are fed back with weighted tap coefficients and added to the received input signal. The tap coefficients are adjusted, to match the inverse of the channel characteristics. Consequently, ISI is removed from the received input signal such that a decision can be made on the received data symbol with a low BER.