白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Methods and apparatus for randomly distributing traffic in a multi-path switch fabric

專利號
US10097479B1
公開日期
2018-10-09
申請人
Juniper Networks, Inc.（US CA Sunnyvale）
發(fā)明人
Philip A. Thomas; Sarin Thomas; Jean-Marc Frailong; Pradeep Sindhu
IPC分類
H04L12/947; H04L12/707; H04L12/935
技術(shù)領(lǐng)域
egress,switch,indicator,module,schedule,status,fabric,stage,data,port
地域： CA CA Sunnyvale

摘要

In some embodiments, an apparatus comprises a schedule module within a switch fabric system. At a first time, the schedule module is configured to access a list of status indicators associated with a group of egress port indicators. The list of status indicators includes a set of status indicators each of which has a value greater than a threshold. The schedule module is configured to randomly select a status indicator from the set of status indicators and configured to reduce the value of the selected status indicator. The schedule module is then configured to send the egress port indicator associated with the selected status indicator such that a data cell is sent from an egress port associated with that egress port indicator. At a second time, when the value of every status indicator from the list of status indicators is not greater than the threshold, the schedule module is configured to increase the value of every status indicator above the threshold.

說明書

In some embodiments, each switch module 212 of the first stage 240 is a switch (e.g., a packet switch, a frame switch, an integrated Ethernet switch and/or a cell switch). The switches are configured to redirect data (e.g., data packets, data cells, etc.) as it flows through the switch fabric 200. In some embodiments, for example, each switch includes multiple ingress ports operatively coupled to write interfaces on a memory buffer (not shown in FIG. 2). Similarly, a set of egress ports are operatively coupled to read interfaces on the memory buffer. In some embodiments, the memory buffer can be a shared memory buffer implemented using on-chip static random access memory (SRAM) to provide sufficient bandwidth for all ingress ports to write one incoming data cell (e.g., a portion of a data packet) or data packet per time period (e.g., one or more clock cycles) and for all egress ports to read one outgoing data cell or data packet per time period. Each switch operates similarly to a crossbar switch that can be reconfigured in subsequent each time period.

權(quán)利要求

1
微信群二維碼
意見反饋