Referring now to FIG. 2A, an adjustment made by the PCB designer to correct the above-noted violation in PCB design 10A as illustrated, in which a signal trace T4B has been moved toward the right edge in next PCB design 10B. Next, as shown in FIG. 2B, the PCB designer has interchanged reference layer R1 and the layer containing reference layer portions R2A, R2B to form PCB design 10C. Another error box 16B has been generated, with associated text (not shown) that describes a violation due to signal trace T3A now extending over reference layer portion R2B, since reference layer portion R2B is not a reference plane associated with the signal carried by signal trace T3A. FIG. 2C illustrates an attempt by the PCB designer to correct the violation indicated by error box 16B in PCB design 10C by removing reference layer portion R2B in next PCB design 10D, but another error box 16C is generated with associated text (not shown) that indicates that signal trace T3A is not completely covered by a reference plane, which can be corrected by either moving signal trace T3A or by extending reference layer portion R2A underneath signal trace T3A.