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Controlled-impedance printed-circuit board (PCB) design with stack-up re-mapping

專利號
US10750616B2
公開日期
2020-08-18
申請人
INTERNATIONAL BUSINESS MACHINES CORPORATION(US NY Armonk)
發(fā)明人
Michael A. Christo; Diana D. Zurovetz; David Green
IPC分類
G06F30/394; H05K3/00; G06F30/398
技術領域
pcb,computer,design,impedance,designer,traces,program,or,in,violation
地域: NY NY Armonk

摘要

A controlled-impedance printed circuit board (PCB) design program allows interactive movement of features from one of the vertically-stacked layers of the design to another layer in a graphical interface. The movement either moves a region of a layer of the PCB design, or moves an entire layer in a layer-swapping operation. The program computes modified widths of circuit traces of the first layer of the controlled-impedance printed circuit board design according to an impedance control value of the controlled-impedance printed circuit board design and according to a new position of the circuit traces caused by a movement of the features of the first layer to the second layer. The program also checks for violation of reference plane requirements for critical signals and warns the designer if such a violation is present.

說明書

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Referring now to FIG. 5, the region move/layer swap processes invoked in steps 43 and 45 of FIG. 3 are illustrated in accordance with an example embodiment that is used for both region moving and layer swapping. First the user selects the “from” and “to” layers to swap (step 60) and the layers or region on the layers are swapped (step 61). New signal trace widths are computed or are adjusted based on a user-defined impedance definition for the signal trace layer, saved and displayed according to the specified characteristic impedance(s) for the traces bearing critical signals (step 62). An inter-feature spacing check is performed (step 63) and if any spacing violations occur (decision 64) then the feature spacing is increased (step 65) by moving a feature. Once the inter-feature spacing check is complete (decision 64), signal referencing is checked (step 66) to ensure that the signal traces are proximate to a correct reference plane. If a referencing violation is present (decision 67) then a reference plane solution process is invoked (step 68), otherwise the process returns to decision 44 or decision 46 of FIG. 3.

權利要求

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