A bus interface may further be included in FIG. 12, and the bus interface may include any quantity of interconnecting buses and bridges, which specifically link together various circuits of one or more processors represented by the processor and a memory represented by the memory. The bus interface may further link together various other circuits, such as a peripheral device, a voltage regulator, and a power management circuit. This is well known in the art, and therefore is not further described in this specification. The bus interface provides an interface. The transceiver provides a unit that communicates with various other devices on a transmission medium. The processor is responsible for bus architecture management and general processing, and the memory may store data used when the processor performs an operation.

In conclusion, according to the method and the apparatus provided in the embodiments of the present invention, after the identification information sent by the first user equipment is obtained, the shared information related to the identification information is determined from shared information published by an associated user equipment, so that the determined shared information related to the identification information is sent to the first user equipment. In addition, the first user equipment obtains the shared information related to the identification information that is sent by the first user equipment, so that the first user equipment is prevented from screening the shared information, and the first user equipment can more efficiently obtain the shared information related to the identification information that is sent by the first user equipment.