At step 940, the index n is again set to n=1, and the UE estimates the strongest interfering signal having not previously been interference-cancelled at the BS. At step 942, the interfering signal is reconstructed and subtracted from the signal composition. After all such interferers have been removed, the remaining signal is processed (decoded) by the UE at step 944.
Exemplary Receiver Apparatus—
The UE apparatus 1000 comprises an application processor subsystem 1012 such as a digital signal processor, microprocessor, field-programmable gate array, or plurality of processing components mounted on one or more substrates 1018. The processing subsystem may also comprise an internal cache memory 1012A. The processing subsystem 1012 is connected to a memory subsystem comprising memory 1014 which may for example, comprise SRAM, FLASH and SDRAM components. The memory subsystem may implement one or a more of DMA type hardware 1014A, so as to facilitate data accesses as is well known in the processor arts.