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Thick conductor built-in type printed wiring board and method for producing same

專利號
US10791633B2
公開日期
2020-09-29
申請人
Panasonic Intellectual Property Management Co., Ltd.(JP Osaka)
發(fā)明人
Akira Ito; Eiichiro Saito; Naohito Fukuya
IPC分類
H05K3/46; H05K1/03; B32B7/027; H05K1/02
技術(shù)領(lǐng)域
conductor,resin,wiring,layer,prepreg,μm,insulating,printed,board,inclusive
地域: Osaka

摘要

A thick conductor built-in type printed wiring board includes a printed wiring board, an insulating resin layer, an insulating base material layer, and a conductor layer. The printed wiring board includes an insulating layer including a cured product of a first resin composition, and a circuit provided on one main surface or both main surfaces of the insulating layer, the circuit having a plurality of conductor wirings each having a thickness ranging from 105 μm to 630 μm, inclusive. The insulating resin layer covers a surface of the printed wiring board on which the circuit is provided, and includes a cured product of a second resin composition and includes no fibrous base material. The insulating base material layer covers the insulating resin layer, and includes a cured product of a third resin composition and a fibrous base material. The conductor layer covers the insulating base material layer. The thick conductor built-in type printed wiring board does not include a void having a diameter of more than or equal to 10 μm inside the thick conductor built-in type printed wiring board.

說明書

It is preferable that at least one surface of first circuit 12 is a matte surface. In this case, one surface of first circuit 12 may be a matte surface and the other surface thereof may be a shiny surface, or both surfaces of first circuit 12 may be the matte surface. When the matte surface of first circuit 12 is disposed to face insulating layer 11, peel strength between first circuit 12 and insulating layer 11 in thick conductor built-in type printed wiring board 1 can be improved due to an anchor effect.

Ten-point average roughness (RZJIS) of the matte surface of the first circuit is not specifically limited, but ranges preferably from 0.5 μm to 5.0 μm, inclusive. Ten-point average roughness (RZJIS) of the shiny surface of the first circuit is not specifically limited, but ranges preferably from 0.5 μm to 2.5 μm, inclusive. On the matte surface, larger number of irregularities that are more precise than those on the shiny surface are formed as compared with the shiny surface.

權(quán)利要求

1
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