FIG. 11 illustrates separate processing blocks for preamble detection and timing estimation according to some embodiments of the present disclosure;

FIG. 12 illustrates preamble detection of interlaced intervals of sub-carriers and with oversampling according to some embodiments of the present disclosure;

FIGS. 13 and 14 illustrate power delay profiles without and with oversampling according to some embodiments of the present disclosure;

FIG. 15 illustrates a miss detection rate versus a Signal to Noise Ratio (SNR) according to some embodiments of the present disclosure;

FIGS. 16 and 17 illustrate a resolution of timing estimate without and with oversampling according to some embodiments of the present disclosure;

FIG. 18 illustrates timing estimation with zero inserting according to some embodiments of the present disclosure;

FIG. 19 illustrates timing estimate errors for various levels of oversampling according to some embodiments of the present disclosure;

FIG. 20 illustrates the computational complexity for timing estimation for various levels of oversampling according to some embodiments of the present disclosure;

FIG. 21 is a block diagram of a wireless device according to some embodiments of the present disclosure;

FIG. 22 is a block diagram of a radio access node according to some embodiments of the present disclosure;