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Electronic control unit

專利號(hào)
US10834856B2
公開日期
2020-11-10
申請(qǐng)人
DENSO CORPORATION(JP Kariya)
發(fā)明人
Hiroyasu Sugiura
IPC分類
H05K1/02; H05K7/20; H05K1/11; H05K3/34; H02K11/33; B62D5/04; H05K3/42; H05K1/18
技術(shù)領(lǐng)域
vias,terminal,substrate,pattern,circuit,layer,connection,ground,soldering,heat
地域: Kariya

摘要

An electronic control unit has a substrate that includes a terminal connection portion that is a through hole that extends through the substrate from a first surface to a second surface. A resist opening along an outer edge of the terminal connection portion exposes a circuit pattern from a surface resist layer. A plurality of vias are disposed at positions adjacent to the resist opening in a heat receiving area to facilitate the transfer of heat during a soldering process from the first surface to the second surface.

說明書

The fifth embodiment is described with reference to FIG. 18. In the present embodiment, a middle layer via 357 on the center side of the terminal connection portion 34 and a middle layer via 358 on the periphery side of the terminal connection portion 34 are formed in the substrate 50. The middle layer via 357 is formed immediately below the inner front side via 351 and the middle layer via 358 is formed immediately below the outer front side via 352.

The substrate 50 also includes back side vias 361 and 362 formed to connect the circuit pattern 66 of the sixth layer L26 and the circuit pattern 65 of the fifth layer L25. The back side vias 361 and 362 are laser vias, and the insides of the vias 361 and 362 are filled with a conductive material (i.e., conductor) such as copper. The second surface 502 sides of the vias 361 and 362 are covered with the surface resist layer 68. In the present embodiment, the back side vias 361 and 362 are aligned with the front side vias 351 and 352 and disposed immediately below the middle layer vias 357 and 358, as shown in FIG. 18. However, the back side vias 361 and 362 are not limited to such a position and may be positioned elsewhere in the substrate 50.

In the present embodiment, the middle layer via 357 is formed immediately below the inner front side via 351, and the middle layer via 358 is formed immediately below the outer front side via 352. Such a configuration better facilitates heat dissipation to the second surface 502.

權(quán)利要求

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