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Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries

專利號(hào)
US10867092B2
公開日期
2020-12-15
申請人
Intel Corporation(US CA Santa Clara)
發(fā)明人
Dror Caspi; Ido Ouziel
IPC分類
G06F30/3323; G06F9/46; G06F9/455; G06F12/1009; G06F12/1027; G06F12/0897; G06F9/52
技術(shù)領(lǐng)域
enclave,tlb,rlp,epoch,in,rar,page,processor,ilp,or
地域: CA CA Santa Clara

摘要

Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

說明書

Turning to FIG. 2, embodiments of a computing system 200 configured for avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer (TLB) entries can resolve the aforementioned issues (and more) associated with evicting pages of protected data or code from an enclave. When a page of protected data or code is being evicted from an enclave, embodiments of computing system 200 described herein can perform TLB tracking without requiring, in most cases, a logical processor to exit from the enclave (e.g., via an asynchronous exit). A request to invalidate a TLB entry for an enclave page may be communicated in the form of a remote action request (RAR) interrupt or signal to logical processors in a system as part of evicting the page from the enclave. Certain logical processors that are running in the enclave and that receive the request may avoid an asynchronous exit from the enclave by invalidating the TLB entries corresponding to enclave pages and adjusting TLB tracking state of the logical processor. These actions may be taken in response to successful condition checks performed on control and state pages associated with the enclave.

權(quán)利要求

1
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