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Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries

專利號(hào)
US10867092B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Dror Caspi; Ido Ouziel
IPC分類
G06F30/3323; G06F9/46; G06F9/455; G06F12/1009; G06F12/1027; G06F12/0897; G06F9/52
技術(shù)領(lǐng)域
enclave,tlb,rlp,epoch,in,rar,page,processor,ilp,or
地域： CA CA Santa Clara

摘要

Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

說(shuō)明書

Embodiments of the instruction(s) referenced herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

FIG. 9 is a block diagram of a register architecture 900 according to one embodiment of the present disclosure. In the embodiment illustrated, there are 32 vector registers 910 that are 512 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-15. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15.

In other words, a vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of a specific vector friendly instruction format operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

權(quán)利要求

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