白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries

專利號
US10867092B2
公開日期
2020-12-15
申請人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Dror Caspi; Ido Ouziel
IPC分類
G06F30/3323; G06F9/46; G06F9/455; G06F12/1009; G06F12/1027; G06F12/0897; G06F9/52
技術領域
enclave,tlb,rlp,epoch,in,rar,page,processor,ilp,or
地域： CA CA Santa Clara

摘要

Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

說明書

In Example A12, the subject matter of any one of Examples A10-A11 can optionally include where adjusting the one or more enclave reference counters includes incrementing a first enclave reference counter for a current epoch by one and decrementing a second enclave reference counter for the prior epoch by one.

In Example A13, the subject matter of any one of Examples A10-A12 can optionally include where, prior to adjusting the enclave entry epoch variable, the remote action handler circuit is to further: obtain a current value of the enclave entry epoch variable; obtain a current value of a global epoch variable; and determine the logical processor entered the enclave mode during the prior epoch based on a comparison of the current value of the enclave entry epoch variable and the current value of the global epoch variable.

In Example A14, the subject matter of any one of Examples A1-A13 can optionally include where the RAR is associated with one of an inter-processor interrupt (IPI) or a RAR signal.

In Example A15, the subject matter of any one of Examples A1-A14 can optionally include where the memory includes an enclave page cache that stores one or more pages at one or more page addresses corresponding to the one or more TLB entries.

權利要求

1
微信群二維碼
意見反饋