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Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries

專(zhuān)利號(hào)
US10867092B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Dror Caspi; Ido Ouziel
IPC分類(lèi)
G06F30/3323; G06F9/46; G06F9/455; G06F12/1009; G06F12/1027; G06F12/0897; G06F9/52
技術(shù)領(lǐng)域
enclave,tlb,rlp,epoch,in,rar,page,processor,ilp,or
地域： CA CA Santa Clara

摘要

Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

說(shuō)明書(shū)

In Example M6, the subject matter of any one of Examples M1-M5 can optionally include where the prior epoch is a period during which a prior value was assigned to a global epoch variable.

In Example M7, the subject matter of any one of Examples M1-M6 can optionally include where the results indicate that the control and state pages associated with the enclave mode are unmodified, unblocked and otherwise accessible to the logical processor.

In Example M8, the subject matter of any one of Examples M1-M7 can optionally include where the control page includes meta information related to a thread running on the logical processor.

In Example M9, the subject matter of any one of Examples M1-M8 can optionally include where at least one state page includes context information associated with a state of the logical processor.

In Example M10, the subject matter of any one of Examples M1-M9 can optionally include where the one or more variables include an enclave entry epoch variable and one or more enclave reference counters.

In Example M11, the subject matter of Example M10 can optionally include where adjusting the enclave entry epoch variable includes setting the enclave entry epoch variable to a current value of a global epoch variable.

In Example M12, the subject matter of any one of Examples M10-M11 can optionally include where adjusting the one or more enclave reference counters includes incrementing a first enclave reference counter for a current epoch by one and decrementing a second enclave reference counter for the prior epoch by one.

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