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Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries

專(zhuān)利號(hào)
US10867092B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Dror Caspi; Ido Ouziel
IPC分類(lèi)
G06F30/3323; G06F9/46; G06F9/455; G06F12/1009; G06F12/1027; G06F12/0897; G06F9/52
技術(shù)領(lǐng)域
enclave,tlb,rlp,epoch,in,rar,page,processor,ilp,or
地域： CA CA Santa Clara

摘要

Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

說(shuō)明書(shū)

In Example M13, the subject matter of any one of Examples M1-M12 can optionally include where, prior to adjusting the enclave entry epoch variable, the method further comprises: obtaining a current value of the enclave entry epoch variable; obtaining a current value of a global epoch variable; and determining the logical processor entered the enclave mode during the prior epoch based on a comparison of the current value of the enclave entry epoch variable and the current value of the global epoch variable.

In Example M14, the subject matter of any one of Examples M1-M13 can optionally include where the RAR is associated with one of an inter-processor interrupt (IPI) or a RAR signal.

In Example M15, the subject matter of any one of Examples M1-M14 can optionally include where the memory includes an enclave page cache that stores one or more pages at one or more page addresses corresponding to the one or more TLB entries.

Example X1 provides an apparatus for avoiding an asynchronous exit from an enclave mode, where the apparatus comprises means for performing the method of any one of the preceding Examples.

In Example X2, the subject matter of Example X1 can optionally include that the means for performing the method comprises at least one processor and at least one memory element.

In Example X3, the subject matter of Example X2 can optionally include that the at least one memory element comprises machine readable instructions that when executed, cause the apparatus to perform the method of any one of the preceding Examples.

In Example X4, the subject matter of any one of Examples X1-X3 can optionally include that the apparatus is one of a computing system, a processing element, or a system-on-a-chip.

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