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Avoiding asynchronous enclave exits based on requests to invalidate translation lookaside buffer entries

專利號(hào)
US10867092B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
Intel Corporation（US CA Santa Clara）
發(fā)明人
Dror Caspi; Ido Ouziel
IPC分類
G06F30/3323; G06F9/46; G06F9/455; G06F12/1009; G06F12/1027; G06F12/0897; G06F9/52
技術(shù)領(lǐng)域
enclave,tlb,rlp,epoch,in,rar,page,processor,ilp,or
地域： CA CA Santa Clara

摘要

Technologies are provided in embodiments including a memory element to store a payload indicating an action to be performed associated with a remote action request (RAR) and a remote action handler circuit to identify the action to be performed, where the action includes invalidating one or more entries of a translation lookaside buffer (TLB), determine that the logical processor entered an enclave mode during a prior epoch, perform one or more condition checks on control and state pages of the enclave mode, and based on results of the one or more condition checks, adjust one or more variables associated with the logical processor to simulate the logical processor re-entering the enclave mode. Specific embodiments include the remote action handler circuit to invalidate an entry of the TLB based, at least in part, on the results of the one or more condition checks.

說(shuō)明書(shū)

When an enclave page is blocked, an ETRACK instruction is performed on a logical processor to advance the epoch by incrementing the global epoch variable to N+1. The global epoch variable divides the timeline so that events occurring before the ETRACK instruction is performed and after the ETRACK instruction is performed can be used to understand whether TLB entries to pages within the enclave might exist. In addition, for each enclave, reference counters can be used to keep track of the number of logical processors running during the current and previous epochs, based on entries into the enclave and exits from the enclave. Furthermore, for each logical processor running in the enclave, the epoch at the time of enclave entry for that logical processor is recorded, for example, in an enclave entry epoch variable (e.g., CR_EV variable).

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