Data processing apparatus, data processing method, and non-transitory storage medium
摘要
說明書
The bus 5A is a data transmission line in a case where the processor 1A, the memory 2A, the peripheral circuit 4A, and the input and output interface 3A transmit and receive data to and from each other. The processor 1A is an arithmetic processing apparatus, such as a central processing unit (CPU) or a graphics processing unit (GPU), for example. The memory 2A is a memory, such as a random access memory (RAM) or a read only memory (ROM), for example. The input and output interface 3A includes an interface for acquiring information from an external apparatus, an external server, or the like. The processor 1A issues a command to each module, and performs calculations based on the calculation results of the modules.
Hereafter, the present example embodiment will be described. Each functional block diagram used in the explanation of the following example embodiments does not show a hardware-unit configuration but shows a block of functional units. Although each apparatus is implemented by one apparatus in these diagrams, the implementation means is not limited thereto. That is, a physically divided configuration or a logically divided configuration may also be adopted. The same components are denoted by the same reference numerals, and the explanation thereof will not be repeated.
