To help provide content, FIG. 26 depicts timing diagram of the binary pulse width modulation emission scheme with two reorderings implemented with the three color channels. This timing diagram shows the relationship between the loading of digital data into the memory 78 that occurs substantially simultaneously to other actions performed by the row driver 60. For example, data loading of the green channel's most significant bits occurs at a time 612 of the emission of the red channel's least significant bit. Comparing FIG. 26 to FIG. 25, just as was described for the fourth quadrant 606D, the row driver 60 permits the sub-pixel 72 to emit light according to the bit-plane represented by data stored in and transmitted from the memory 78. As is indicated on the timing diagram, the total emission period for all three color channels is approximately equal to three time times the channel-specific emission period.
An example embodiment of a pixel operated by a row driver 60 to follow a binary pulse width modulation reordering emission scheme including memory circuitry 560, MWRs 406, MSELs 410, inverter pairs 408, inverter pair 498, a SR latch 562 coupled to analog driver circuitry 561 is shown in FIG. 27. This figure is meant to be example and not limiting, for example, a variety of pixel circuitry and analog driving circuitry may be used in conjunction with memory circuitry 560 and memory-in-pixel techniques. FIG. 27 shows an example of memory circuitry 560 as applied to a digital mirror display (DMD).
