Generally, the depicted memory circuitry 560 operates to receive DATA 412 corresponding to a target gray level for a color channel of the pixel 70 corresponding to the memory circuitry 560. As illustrated, the memory circuitry 560 includes different color groups of memory for each color channel. In this embodiment, the pixel 70 has memory circuitry for each color channel instead of unique sub-pixels 72 for each color channel (e.g., R-G-B). A row driver 60 may operate the color channels via enabling a color group (CG) signal 564. Upon activation of a CG transistor (MCG) 565, stored DATA 412 transmits towards the analog driver circuitry 561. The row driver 60 may permit one color channel to transmit at a time. Thus, the depicted memory circuitry 560 facilitates color sequential output from individual memory circuitry to shared output circuitry coupled to a DMD electrode.