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Systems and methods for memory circuitry in an electronic display

專利號(hào)
US10867548B2
公開日期
2020-12-15
申請(qǐng)人
Apple Inc.（US CA Cupertino）
發(fā)明人
Tien-Chien Kuo; Kanghoon Jeon; Yingkan Lin; Bilin Wang; Ivan Knez; Stanley Bo-Ting Wang; Chun-Yao Huang
IPC分類
G09G3/32; G09G3/36; G09G3/20; G09G3/3275; G09G3/3258
技術(shù)領(lǐng)域
pixel,driver,emission,bit,circuitry,data,sub,row,memory,image
地域： CA CA Cupertino

摘要

An electronic display may include a memory formed in an active area of the electronic display or formed in integrated circuitry of the electronic display that is outside of the active area. The memory may store a digital data signal indicative of a value within a data range. The electronic display may include a driver disposed in the active area, where the driver may generate one or more analog electrical signals in response to the digital data signal. The electronic display may also include a light-modulating device disposed on the active area, where the light-modulating device may emit light based at least in part on the one or more analog electrical signals.

說明書

A row driver 60 may operate the depicted memory circuitry 560 similar to memory circuitry 560 of FIG. 23. Thus, for an example of two reorderings, the row driver 60 may operate in four different operational modes, where the operational mode is selected based on the gray level value of DATA 412. After writing DATA 412 to the inverting pairs 408, the row driver 60 operates memory circuitry 560 to transmit stored DATA 412 to SR latch 562 a bit at a time to drive a DMD electrode through analog driver circuitry 561. The row driver 60 may reorder DATA 412 to create a single pulse width modulated signal from a binary pulse width modulation emission data by selectively enabling and/or disabling CG signals 564 (e.g., enabling 564B to transmit red data corresponding to bit-plane 7) by driving memory circuitry 560 with different operational modes.

For example, and as described above, for a first operational mode (e.g., corresponding to gray levels between zero and the gray level threshold), the row driver 60 may reset the S node, precharge, enable Sel[n] 415B and enable SET signal 602, precharge, enable Sel[n-1] 415 and enable SET signal 602, precharge, and enable Sel[0] 415A. The row driver may repeat the first operational mode for each bit of DATA 412, incrementing from a first bit, DATA[0] 412A until reaching DATA[n-2] (e.g., where 2 corresponds to a number of reordering). The row driver 60 may operate as described in discussions for FIG. 23 while in the second, third, and fourth operational modes.

權(quán)利要求

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