As briefly discussed in FIG. 21, slight adjustments to the memory-in-pixel techniques may be generally applied to permit moving the memory 78 into a smart buffer, as opposed to or in addition to including the memory 78 in the sub-pixel 72 itself. FIG. 29 shows this generally with a memory-in-pixel architecture electronic display 700 and a smart buffer architecture electronic display 702. The memory-in-pixel architecture electronic display 700 includes, as depicted, memory 78 in each sub-pixel 72 located in an active area 704 of the electronic display 18, where the active area 704 includes all the light-emitting components of the electronic display and communicative couplings to support data transmission to the light-emitting components. In the memory-in-pixel architecture electronic display 700, digital data is transmitted from memory 708 (e.g., DRAM or SRAM memory) to each respective sub-pixel 72 for localized buffering in the memory 78. In some embodiments, the digital data transmits from the memory 708 to a source area 710 before transmission into the memory 78 for localized buffering (e.g., buffering within the sub-pixel 72). However, substantially similar memory as memory 78 may be included in a smart buffer 712 of the smart buffer architecture electronic display 702 to still eliminate, or at least reduce, a reliance upon a frame buffer but additionally remove the memory 78 from the active area 704. By moving the memory 78 into a smart buffer 712, the row driver 60 may use operate an input latch 714 and an output latch 716 to arbitrate light emission from each sub-pixel 72 via analog out circuitry, for example, the driver 80. Here, the smart buffer 712 may represent any suitable buffer memory disposed in an integrated circuit of the electronic display 18 but outside of the active area of the electronic display 18.
