Systems and methods for memory circuitry in an electronic display
摘要
說明書
However, the display system 52 receives the image data 56 at the timing controller 54. The timing controller 54 may use the image data 56 to determine clock signals used to provision the image data 56 to the memory-in-pixel pixel array 69. The timing controller 54 transmits the image data 56 to the row driver 60 and/or the column driver 62 to program the memory of the pixel array 69 with digital data signals associated with the image data 56, where the digital data signals indicate the emission brightness/gray level for the pixels of the pixel array 69.
By implementing memory-in-pixel systems and methods, the display system 52 may reduce a bandwidth of signals communicated over communicative link 68, for example, when compared to a bandwidth of signals communicated over the communicative link 64. In some instances, a single channel of image data 56 may transmit through the communicative link 64 (e.g., red channel), as opposed to all channels being simultaneously transmitted to the pixel array 66 (e.g., red-green-blue channels). In this way, the communicative link 68 communicates image data 56 associated with a respective pixel of the pixel array 66 for the red channel, the green channel, and the blue channel at different times, causing a decrease in an overall bandwidth of signals used to communicate image data 56. Decreasing an overall bandwidth of the communicative link 68 may lead to a decrease in power consumption of the electronic device 10 because processing less data (e.g., a single channel of image data) at a given time may consume fewer processing resources than processing more data (e.g., three channels of image data).
