Systems and methods for memory circuitry in an electronic display
摘要
說明書
Explaining operation of the display system 52A, the timing controller 54 receives image data 56 corresponding to a next image to be displayed on an electronic display having the pixel array 69. The timing controller 54 generates control signals and/or clocking signals responsive to the image data 56 and transmits signals related to operating rows of pixels 70 to the row driver 60 and transmits signals related to operating columns of pixels 70 to column driver 62. The row driver 60 is responsive to the signals associated with the image data 56 transmitted from the timing controller 54 and generates emit control signals 82 and write control signals 84 for each red-green-blue (RGB) channel. The column driver 62, also being responsive to the signals associated with the image data 56 transmitted from the timing controller 54, generates image data 86 to be transmitted to the memory 78 of each of the pixels 70. The column driver 62 may generate image data 86 in response to the signals associated with the image data 56 and/or the image data 56, in some embodiments, however, image data 56 transmits to each of the pixels 70 as image data 86. The column driver 62 generates data of size N bits for each sub-pixel 72, matching a size of the memory 78 which is also size N bits.
