In the example embodiment of the display system 52B in FIG. 7, the pixel array 69 includes a multiplexing circuit 96 that receives image data 98 of size N bits from the column driver 62. The multiplexing circuit 96 is responsive to a respective multiplexing control signal (MUX control signal) 100 of multiplexing control signals 101. The MUX control signal 100 may cause the multiplexing circuit 96 to output data to a sub-pixel 72 of a pixel 70. In this way, the column driver 62, through emission of the MUX control signal 100, may operate to program a sub-pixel 72 (e.g., one color channel) of a pixel 70 at a time via, for example, a communicative coupling 94. For the pixel array 69, various embodiments of sub-pixel 72 circuits may be used.
An example of an embodiment of a sub-pixel 72 implementing memory-in-pixel techniques includes a memory 78, a driver 80, a current source 102, a LED 103, a switch 104, and a counter 105, where the sub-pixel 72 receives a variety of signals including image data 98, a bit-plane clock 106, a reset signal 108, a common voltage 110, a first reference voltage 112, a second reference voltage 114, and a data clock 116, is shown in FIG. 8. It should be appreciated that the depicted sub-pixel 72 is merely intended to be illustrative and not limiting. For example, memory 78 is depicted as a 12-bit register but may be any suitable memory circuit to store any suitable number of bits.
