Systems and methods for memory circuitry in an electronic display
摘要
說明書
The depicted sub-pixel 72 may emit according to a binary pulse width modulation emission scheme. To explain operation of the sub-pixel 72, image data 98 transmits to the memory 78 from, for example, a column driver 62. Additionally or alternatively, image data 92, image data 56, or any suitable image data may be transmitted to the memory 78 for storage. Upon receiving the image data 98, the memory 78 stores the image data 98 clocked in by the data clock 116. The image data 98 may be represented by binary data such that any given bit may equal a zero, “0,” or a one, “1”, where a 0 corresponds to a logical low voltage value for the system and a 1 corresponds to a logical high voltage value for the system. The memory 78 may output the image data 98 to the switch 104, for example, bit by bit in order from least significant bit to most significant bit, according to a clocking signal generated by a combination of the counter 105 and the bit-plane clock 106.
As shown, a bit-plane clock 106 has clocking time periods that increase over time to correspond to a level of influence of a particular bit in the image data 98. In this way, a least significant bit of the image data 98 may be associated with a smaller clocking time period than a most significant bit of the image data 98.
