Referring back to FIG. 14, the timing diagram 279 shows, after the initialization process, the row driver 60 disables the CSinitialization signal 243 to perform a charging process to the sub-pixel 72. During the charging process, the Vdata signal 242, the CSauto.zero signal 237, the CSimage.data signal 247, the CSselect signal 280, and the CSreset signal 235 remain at their previous state. The timing diagram 279 shows the Vdata signal 242 at a high voltage level for the sub-pixel 72 circuit (DVDD), for example, corresponding to a logical high value in binary data for the sub-pixel 72 and/or the electronic device 10. In some embodiments, DVDD is equal to a voltage value of the Vreference signal 246.
Referring back to FIG. 13, the control signals outputted by the row driver 60 activate and/or deactivate various switching elements to execute a charging process. Upon the disabling of the CSinitialization signal 243 and the deactivation of the MINI 220, the capacitor 232 charges based on the Vdata signal 242 and the Vreference signal 246. Charging the capacitor 232 may enable the current drive 270 to remain in use during the emission process even while the MSEL 224 is deactivated. In some embodiments, the capacitor 232 holds the voltage value of the Vdata signal 242 after the charging process such that the MDR 222 may remain activated throughout the emission process—permitting the current drive 270 to produce a constant driving current through the LED 230 for emission.
