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Systems and methods for memory circuitry in an electronic display

專利號
US10867548B2
公開日期
2020-12-15
申請人
Apple Inc.（US CA Cupertino）
發(fā)明人
Tien-Chien Kuo; Kanghoon Jeon; Yingkan Lin; Bilin Wang; Ivan Knez; Stanley Bo-Ting Wang; Chun-Yao Huang
IPC分類
G09G3/32; G09G3/36; G09G3/20; G09G3/3275; G09G3/3258
技術(shù)領(lǐng)域
pixel,driver,emission,bit,circuitry,data,sub,row,memory,image
地域： CA CA Cupertino

摘要

An electronic display may include a memory formed in an active area of the electronic display or formed in integrated circuitry of the electronic display that is outside of the active area. The memory may store a digital data signal indicative of a value within a data range. The electronic display may include a driver disposed in the active area, where the driver may generate one or more analog electrical signals in response to the digital data signal. The electronic display may also include a light-modulating device disposed on the active area, where the light-modulating device may emit light based at least in part on the one or more analog electrical signals.

說明書

FIG. 24E is a bit-plane graph corresponding to three reorderings implemented in the memory circuitry of FIG. 23, in accordance with an embodiment;

FIG. 24F is an error graph corresponding to three reorderings implemented in the memory circuitry of FIG. 23, in accordance with an embodiment;

FIG. 24G is a bit-plane graph corresponding to an ideal case of reordering implemented in the memory circuitry of FIG. 23, in accordance with an embodiment;

FIG. 24H is an error graph corresponding to an ideal case of reordering implemented in the memory circuitry of FIG. 23, in accordance with an embodiment;

FIG. 25 is a bit-plane graph illustrating the bit-plane graph of FIG. 24C over time and with an inclusion of additional color channels, in accordance with an embodiment;

FIG. 26 is a timing diagram illustrating a loading and emission process associated with a third quadrant of the bit-plane graph of FIG. 25, in accordance with an embodiment;

FIG. 27 is a circuit diagram of an embodiment of the memory circuitry of FIG. 23 implemented for use in a digital mirror display, in accordance with an embodiment;

權(quán)利要求

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