Systems and methods for memory circuitry in an electronic display
摘要
說(shuō)明書(shū)
The memory circuitry 400B is depicted as including one or more write enabling transistors (MWRs) 406, one or more inverter pairs 408, and one or more selection transistors (MSELs) 410. DATA 412 is received into the memory circuitry 400B from, for example, a column driver 62. To transmit DATA 412 into the memory circuitry 400B, a row driver 60 may enable a write_en signal 406 and an inverse of the write_en signal (inverse write_en) 444 to enable bitwise memory storage of the DATA 412. For example, the row driver 60 may enable storage of a last bit of DATA 412 in the inverter pair 408B by activating MWR 406D and/or MWR 406C. Thus, the row driver 60 and the column driver 62 may operate to enable bitwise transmission and storage of DATA 412 into the memory circuitry 400B.
Upon storage of the DATA 412 in the inverter pairs 408, the memory circuitry 400B stores the DATA 412 value until the row driver 60 selects a respective bit for transmission. Prior to selecting the respective bit for transmission, the row driver 60 precharges the sense amplifier 440 via enabling of a precharge (Precharge) signal 416. By precharging the sense amplifier 440 and subsequent analog driver circuitry 442, the sub-pixel's 72 responsiveness to transmitted electrical signals may improve when compared to a sub-pixel 72 not precharged. As described prior, precharging a sub-pixel 72 may make switching states easier and less demanding on circuitry (e.g., by increasing circuitry responsiveness).
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