To summarize operation of the sub-pixel 72 embodiment of FIG. 18 and of FIG. 17, an example of a process 461 for controlling operation of a sub-pixel 72 coupled to memory circuitry 400 is described in FIG. 19. Generally, the process 461 includes loading memory with a current bit (block 462), determining if the current bit is the last bit to be loaded into memory (block 464), in response to the current bit not being the last bit, loading the memory with a next current bit (block 462), and in response to the current bit being the last bit, enabling selection signal to permit reading of a bit from the memory (block 466), waiting for the bit to cause emission in pixel circuitry (block 468), and determining if the bit is a last bit to be read from memory (block 471). In response to the bit being the last bit, completing the display cycle (block 472) and in response to the bit not being the last bit, enabling a next selection signal to permit reading of a next bit from the memory (block 466). In some embodiments, the process 461 may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium, such as one or more storage devices 14, using processing circuitry, such as the processing core complex 12. Additionally or alternatively, the process 461 may be implemented at least in part based on circuit connections formed in display controlling circuitry, such as a row driver 60, a column driver 62, and/or a timing controller 54.
