Systems and methods for memory circuitry in an electronic display
摘要
說明書
In the depicted sub-pixel 72, DATA 412 of size n bits is received into the memory circuitry 491 following a similar process as described earlier, that is, a row driver 60 operates to enable a write_en signal 494 to cause transmission of DATA 412 into the inverter pairs 496. In some embodiments, the row driver 60 operates in tandem with a column driver 62 to cause parallel transmission of all bits associated with DATA 412 into the inverter pairs 496 by enabling write_en signals 494 at the same time. Additionally or alternatively, the row driver 60 may cause bitwise transmission of bits associated with DATA 412 through selectively enabling write_en signals 494, for example, loading a bit into inverter pair 496A by selectively enabling write_en signal 494A to cause transmission of the first bit of DATA 412.
