The third switch transistor M3 includes a first electrode configured to receive an initialization signal Vinit, a control electrode configured to receive a reset signal Re, and a second electrode connected with the second terminal of the storage capacitor Cst.

The fourth switch transistor M4 includes a control electrode configured to receive the scan signal Scan, a first electrode connected with a control electrode of the driver transistor M0, and a second electrode connected with the second electrode of the driver transistor M0.

The fifth switch transistor M5 includes a first electrode configured to receive the high-voltage signal VDD, a control electrode configured to receive the reset signal Re, and a second electrode connected with the first terminal of storage capacitor Cst.

The sixth switch transistor M6 includes a control electrode configured to receive the light-emission control signal EM, a first electrode connected with the second electrode of the driver transistor M0, and a second electrode connected with the first terminal of the light-emitting element L.

Optionally in the pixel circuit above, the first terminal of the light-emitting element may be an anode, and the second terminal thereof may be a cathode.

Optionally the control electrodes may be gates, the first electrodes may be sources or drains, and the second electrodes may be drains or sources, dependent upon different types of the respective switch transistors above, and different signals input thereto, although the embodiment of the disclosure will not be limited thereto.