Since each frame of image is only displayed in the light emission phase T3, and there is a short time interval between the preceding frame and the current frame, the high-voltage signal VDD received at the first electrode of the driver transistor M0 before the light emission phase T3 in the current frame may be regarded as the high-voltage signal VDD received at the first electrode of the driver transistor M0 in the preceding frame, that is, the signal received at the first electrode of the driver transistor M0 in the initialization phase T1 and the data write phase T2 in the current frame is the high-voltage signal VDD at voltage V_dd(1) in the preceding frame, and the signal received at the first electrode of the driver transistor M0 in the light emission phase T3 in the current frame is the high-voltage signal VDD at voltage V_dd(2) in the current frame.

In the initialization phase T1, the reset signal Re at a low level controls the third switch transistor M3 and the fifth switch transistor M5 to be turned on. The third switch transistor M3 which is turned on provides the initialization signal Vinit for the second terminal of the storage capacitor Cst and the control electrode of the driver transistor M0, to initialize voltage of the storage capacitor Cst and the control electrode of the driver transistor M0. The fifth switch transistor M5 which is turned on provides the first terminal of the storage capacitor Cst with the high-voltage signal VDD at the voltage V_dd(1).