The sub-pixel sub-unit circuit includes the data writing sub-circuit 11, the storage capacitor sub-circuit 12, the driving transistor DTFT and the light emitting element 13. The sub-pixel sub-unit circuit is connected to at least two display signal lines and at least two display signal terminals.
The pixel compensation sub-unit circuit includes the reading control sub-circuit 21 and the photosensitive sub-circuit 22 configured to convert the light emitted from the light emitting element 13 to an electrical signal. The pixel compensation sub-unit circuit is connected to at least two compensation signal lines and a compensation signal terminal.
The at least two display signal lines may include a first gate line Scan1 and a data line Data; the at least two display signal terminals may include a first voltage input terminal and a second voltage input terminal. The at least two compensation signal lines may include a second gate line and a reading line RL. The plurality of compensation signal terminals may include a third voltage input terminal.
The pixel compensation sub-unit circuit may further include a compensation control sub-circuit 501. The compensation control sub-circuit 501 is connected to the reading line RL, and is connected to a data driving sub-circuit 502 connected to the data line Data.
In the fifth example of the pixel unit circuit provided in the present disclosure, the second gate line and the first gate line Scan1 are the same gate line.