Thus, the first node N1, the second node N2, and the anode are all connected during the period ta3 to ta4 after the second node N2 and the anode are initialized back to the first voltage level ELVDD_L, and accordingly, the voltage of the first capacitor Cst, remaining even after the period ta2 to ta3, is initialized again.
During a period ta5 to tab, the scan signals S[1] to S[n] have the gate-on voltage level VGL, and then may have the gate-off voltage level VGH until before the threshold voltage compensation period PA2.
In addition, during the period ta5 to tab, the scan signals S[1] to S[n] have the gate-on voltage level VGL, and then may maintain the gate-on voltage level VGL until the threshold voltage compensation period PA2.