The data voltages according to the data signals, which have been written during the previous frame period, remain in the first nodes N1 of the respective pixels PX even after light emission is terminated. According to the illustrated embodiment, a first operation that connects all of the first node N1, the second node N2, and the anode and a second operation that initializes the second node N2 and the anode to the first power ELVDD of the first voltage level ELVDD_L may be iteratively performed to initialize the first node N1. In the timing diagram of FIG. 3, the first operation is performed three times and the second operation is performed three times, but the first node N1 may be initialized only by sequentially performing the first operation, the second operation, and the first operation. Alternatively, the first node N1 may be initialized by alternately iteratively performing the first operation and the second operation during the initialization period PA1.

In the threshold voltage compensation period PA2, the first power ELVDD has a third voltage level ELVDD_H, the initialization power VINT has a fifth voltage level VINT_H, and the second power ELVDD has a seventh voltage level ELVSS_H. The scan signals S[1] to S[n] may have the gate-on voltage level VGL. Accordingly, the gate of the first transistor T1 and the second end of the first transistor T1 are connected by the turned-on second transistor T2 and the turned-on third transistor T3, and accordingly, the first transistor T1 can be diode-connected.