The second transistor T22 includes a gate connected to a i-th scan line Si, a first end connected to a j-th data line Dj, and a second end connected to the second node N22. The second transistor T22 transmits a data voltage according to the data signal D[j], which has been transmitted through an j-th data line Dj in response to a corresponding scan signal S[i], which has been transmitted through a i-th scan line Si.

The third transistor T23 includes a gate connected to the i-th scan line Si, and opposite ends that are respectively connected to the gate and the second end of the first transistor T21. The third transistor T23 operates in response to a corresponding scan signal S[i] transmitted through the i-th scan line Si. A turned-on third transistor T23 connects the gate and the second end of the first transistor T21 such that the first transistor T21 is diode-connected.

When the first transistor T21 is diode-connected, a voltage acquired by compensating a data voltage applied to the first end of the first transistor T21 by as much as the threshold voltage of the first transistor T21 is applied to the gate of the first transistor T21. Since the gate of the first transistor T21 is connected to the first end of the first capacitor Cst, the voltage is maintained by the first capacitor Cst. The gate of the first transistor T21 maintains the voltage to which the threshold voltage of the first transistor T21 is applied, and therefore, a driving current flowing to the first transistor T21 is not affected by the influence of the threshold voltage of the first transistor T21.