That is, since after the second node N22 and the anode are initialized to the first level ELVDD_L, the first node N21 and the anode area connected during the period tc1 to tc2, and thus the voltage of the first capacitor Cst, remaining even after a light emission period of a previous frame period, is initialized.

During a period tc2 to tc3, the light emission control signals EM[1] to EM[n] have the gate-on voltage level VGL and the scan signals S[1] to S[n] have the gate-off voltage level VGH. The anode is initialized to a voltage, which is acquired by reflecting the threshold voltage of the first transistor T21 at the first level ELVDD_L by the turned-on fourth transistor T24 and the turned-on first transistor T21.

Next, during a period tc3 to tc4, the scan signals S[1] to S[n] again have the gate-on voltage level VGL and the light emission control signals EM[1] to EM[n] again have the gate-off level VGH.

Accordingly, after the second node N22 and the anode are initialized again by the first power ELVDD of the first level ELVDD_L, the first node N21 and the anode are connected during a period tc3 to tc4, and therefore the voltage of the first capacitor Cst, remaining even after the period tc2 to tc3, is initialized again.