Let M be the number of signal lines 124 output from one selection circuit 200, and N be the number of selection circuits 200. In this case, the total number of signal lines 124 is M×N. The arrangement shown in FIGS. 3A and 3B shows an example in which each of the plurality of display blocks 126 includes nine signal lines 124. For this reason, in one selection circuit 200, to switch the nine signal lines 124 to enable output of an image signal, the switching unit 203 is provided with nine switches SW configured to select the signal line 124 in the one selection circuit 200, as shown in FIG. 3B. Additionally, in a case of the arrangement shown FIGS. 3A and 3B, an image signal write operation is performed nine times using the switches SW in one horizontal scanning period in which the image signals are supplied to the pixels 110 arranged in the row direction among the plurality of pixels 110 arranged in one display block 126.