A display apparatus in which selection circuits and display blocks are arranged is provided. Each of the display blocks include signal lines extending in a column direction, and pixels connected to the signal lines and arranged in a matrix in the column direction and in a row direction crossing the column direction. Each of the selection circuits selects a signal line in a predetermined order to supply an image signal among the signal lines such that the image signal is written in each of the pixels arranged in the row direction among the pixels. A time to select at least one signal line among the signal lines and supply the image signal is different from a time to select a signal line other than the at least one signal line among the signal lines and supply the image signal.
This application claims the benefit of Japanese Patent Application No. 2018-095634, filed May 17, 2018, which is hereby incorporated by reference herein in its entirety.