In the arrangement shown in FIG. 2, a PMOS transistor is used for each transistor. However, the present invention is not limited to this, and an arrangement using n-channel transistors (NMOS transistors) may also be employed. In addition, the driving circuit is not limited to a so-called 4Tr2C circuit arrangement including four transistors and two capacitive elements. In addition, as each transistor, a transistor formed on a silicon wafer may be used, or a thin film transistor formed on a semiconductor film deposited on a glass substrate may be used.

In the pixel 110, the selection transistor 113 is rendered conductive in response to a write signal applied from the vertical driving circuit 103 to the gate electrode via the scanning line 121. By this operation, an image signal or a reference voltage according to luminance information is sampled from the signal line 124. When the reference voltage is sampled from the signal line 124, a threshold voltage variation in the driving transistor 112 of each pixel can be corrected, and a luminance variation in each pixel caused by the threshold voltage variation can be reduced. The image signal or the reference voltage is applied to the gate electrode of the driving transistor 112 and also held by the capacitive element 116.