Liquid crystal device, liquid crystal device driving method, and electronic apparatus
摘要
說明書
The liquid crystal device 100 is supplied with display data (Vi), a horizontal synchronizing signal (Hsync), a vertical synchronizing signal (Vsync), and a reference clock signal (DCLK). In addition to these signals, a reference voltage (VSS), a driving voltage (VDD) or the like is supplied to drive the individual circuits described above, although illustration is not given in
The display data (Vi), the horizontal synchronizing signal (Hsync), the vertical synchronizing signal (Vsync), and the reference clock signal (DCLK) are input into the display signal output circuit 111. Based on these signals, the display signal output circuit 111 generates a scanning signal (not illustrated in
The vertical synchronizing signal (Vsync) and the reference clock signal (DCLK) are input into the signal generation circuit 113. Based on these signals, the signal generation circuit 113 generates a common signal (COM signal) and a polarity signal. The COM signal is a signal that varies at a first period between a first potential and a second potential that is smaller than the first potential, and is supplied to the counter electrode 23. The polarity signal is a logic signal for controlling a polarity of AC signals relating to the driving method for the liquid crystal device 100 that will be described later, and is supplied to each of the display signal output circuit 111, the control circuit 114, and the driving circuit 115.
