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Liquid crystal device, liquid crystal device driving method, and electronic apparatus

專利號
US10867567B2
公開日期
2020-12-15
申請人
SEIKO EPSON CORPORATION（JP Tokyo）
發(fā)明人
Satoshi Yatabe; Naoki Tomikawa
IPC分類
G09G3/36; G02F1/1343
技術(shù)領(lǐng)域
potential,electrode,signal,driving,crystal,com,in,ac,liquid,polarity
地域： Tokyo

摘要

A liquid crystal device includes, peripheral electrodes including three electrodes for ion trapping, and a transistor coupled to each of the three electrodes. A common signal (COM signal) that varies between a first potential and a second potential in a first period is applied to a counter electrode. A driving signal that varies between a third potential and a fourth potential is input to the transistor. The driving signal is coupled to or uncoupled from the peripheral electrodes by the transistor in a unit of a duration equal to or less than ? of the first period. AC signals varying between a positive-polarity potential and a negative-polarity potential, with a potential of the common signal being a reference, in a second period longer than the first period, are applied to the three electrodes of the peripheral electrodes, in a state where phases of the AC signals are shifted mutually.

說明書

In this exemplary embodiment, the multiplexer 112, these three transistors 131, 132, and 133, the wiring line 116 to which a COM signal is supplied, and the three holding capacitors 141, 142, and 143 are provided on the element substrate 210 of the liquid crystal panel 250. Similar to the liquid crystal device 100 according to the above described first exemplary embodiment, the display signal output circuit 111, the signal generation circuit 113, the control circuit 114, and the driving circuit 115 are included in a driving IC 103 (see FIG. 1) mounted on an FPC 102. Any of the display signal output circuit 111, the signal generation circuit 113, the control circuit 114, and the driving circuit 115, or part of these circuits may be provided on the element substrate 210.

The liquid crystal device 200 is supplied with display data (Vi), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a reference clock signal (DCLK). In addition to these signals, a reference voltage (VSS), a drive voltage (VDD), or the like is supplied to drive the individual circuits described above, although illustration is not given in FIG. 13.

權(quán)利要求

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