Liquid crystal device, liquid crystal device driving method, and electronic apparatus
摘要
說明書
The display data (Vi), the horizontal synchronization signal (Hsync), the vertical synchronization signal (Vsync), and the reference clock signal (DCLK) are input into the display signal output circuit 111. Based on these signals, the display signal output circuit 111 generates a scanning signal (not illustrated in
The vertical synchronization signal (Vsync) and the reference clock signal (DCLK) are input into the signal generation circuit 113. Based on these signals, the signal generation circuit 113 generates a common signal (COM signal) and a polarity signal. The COM signal is a signal that varies in a first period between the first potential and the second potential that is smaller than the first potential, and is supplied to the counter electrode 23B. The polarity signal is a logic signal for controlling polarity of an AC signal relating to the driving method for the liquid crystal device 200 that will be described later, and is supplied to each of the display signal output circuit 111, the control circuit 114, and the driving circuit 115.
The vertical synchronization signal (Vsync), the reference clock signal (DCLK), and the polarity signal are input into the control circuit 114. Based on these signals, the control circuit 114 generates a control signal relating to switching control (couple/uncouple) of the first transistor 131, the second transistor 132, and the third transistor 133.
